features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected ? high peak output current: dual 15a peak ? wide operating range: 8v to 30v ? rise and fall times of <3ns ? minimum pulse width of 6ns ? ability to disable output under faults ? high capacitive load drive capability: 4nf in <5ns ? matched rise and fall times ? 32ns input to output delay time ? low output impedance ? low supply current applications ? driving rf mosfets ? class d or e switching amplifier drivers ? multi mhz switch mode power supplies (smps) ? pulse generators ? acoustic transducer drivers ? pulsed laser diode drivers ? dc to dc converters ? pulse transformer driver first release copyright ? ixys corporation 2001 patent pending IXDD415SI dual 15 ampere low-side ultrafast mosfet driver figure 1 - functional diagram inb (8) ina (7) ena (6) enb (9) outa (22, 23, 24) outb (19, 20, 21) 200k 200k gnd (25, 26) vcc (11, 12) vcc (13, 14) vcc (3, 4) vcc (1, 2) gnd (15, 16) gnd (17, 18) gnd (27, 28) general description the ixdd415 is a dual cmos high speed high current gate driver specifically designed to drive mosfets in class d and e hf rf applications, as well as other applications requiring ultrafast rise and fall times or short minimum pulse widths. each output of the ixdd415 can source and sink 15a of peak current while producing voltage rise and fall times of less than 3ns. the outputs of the ixdd415 may be paralleled, producing a single output of up to 30a with comparable rise and fall times. the input of the driver is compatible with ttl or cmos and is fully immune to latch up over the entire operating range. designed with small internal delays, cross conduction/current shoot-through is virtually eliminated in the ixdd415. its features and wide safety margin in operating voltage and power make the ixdd415 unmatched in performance and value. the ixdd415 has two enable inputs, ena and enb. these enable inputs can be used to independently disable either of the outputs, outa or outb, for added flexibility. additionally, the ixdd415 incorporates a unique ability to disable the output under fault conditions. when a logical low is forced into the enable inputs, both final output stage mosfets (nmos and pmos) are turned off. as a result, the output of the ixdd415 enters a tristate mode and achieves a soft turn-off of the mosfet when a short circuit is detected. this helps prevent damage that could occur to the mosfet if it were to be switched off abruptly due to a dv/dt over-voltage transient. the ixdd415 is available in a 28 pin so package (IXDD415SI), incorporating dei's patented (1) rf layout techniques to minimize stray lead inductances for optimum switching performance. (1) dei u.s. patent #4,891,686
2 IXDD415SI parameter value supply voltage 30v all other pins -0.3v to v cc + 0.3v power dissipation t ambient 25 o c 1w t case 25 o c 12w derating factors (to ambient) 28-pin soic 0.1w/ o c storage temperature -65 o c to 150 o c soldering lead temperature (10 seconds maximum) 300 o c unless otherwise noted, t a = 25 o c, 4.5v v cc 25v . all voltage measurements with respect to gnd. ixdd415 configured as described in test conditions . electrical characteristics absolute maximum ratings (note 1) operating ratings parameter value maximum junction temperature 150 o c operating temperature range -40 o c to 85 o c thermal impedance (junction to case) 28 pin soic (si) ( jc ) 0.75 o c/w (1) refer to figures 2a and 2b specifications subject to change without notice symbol parameter test conditions min typ max units v ih high input voltage 3.5 v v il low input voltage 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh output resistance @ o utput h igh i out = 10ma, v cc = 15v 0.8 1.2 ? r ol output resistance @ o utput low i out = 10ma, v cc = 15v 0.8 1.2 ? i peak peak output current v cc = 15v, each output 15 a i dc continuous output current 2 a v en enable voltage range -0.3 vcc + 0.3 v v enh high en input voltage 2/3 vcc v v enl low en input voltage 1/3 vcc v f max maximum frequency c l =1.0nf vcc=15v, max cw frequency lim ited b y package pow er dissipation 45 mhz t r r ise tim e (1) c l =1nf vcc=15v v oh =2v to 12v c l =4nf vcc=15v v oh =2v to 12v 2.5 4.5 ns ns t f f all tim e (1) c l =1nf vcc=15v v oh =2v to 12v c l =4nf vcc=15v v oh =2v to 12v 2.0 3.5 ns ns t ondly on-time propagation delay (1) c l =4nf vcc=15v 32 38 ns t offdly off-time propagation delay (1) c l =4nf vcc=15v 29 35 ns p wmin minimum pulse width fw hm c l =1nf +3v to +3v c l =1nf 5.0 7.0 ns ns t enol enable to output low delay time vcc=15v 80 ns t enoh enable to output high delay time vcc=15v 170 ns t dold disable to output low disable delay time vcc=15v 30 ns t dohd disable to output high disable delay time vcc=15v 30 ns v cc power supply voltage 8 15 30 v i cc power supply current v in = 3.5v v in = 0v v in = + v cc 1 0 3 10 10 ma a a
3 IXDD415SI pin description note 1: operating the device beyond parameters with listed ?absolute maximum ratings? may cause permanent damage to the device. typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. the guaranteed specifications apply only for the test conditions listed. exposure to absolute maximum rated conditions for extended periods may affect device reliability. caution: these devices are sensitive to electrostatic discharge; follow proper esd procedures when handling and assembling this component. pin # symbol function description 1-4 11-14 vcc supply voltage positive power-supply voltage input. this pin provides power to the entire chip. the range for this voltage is from 8v to 30v. 7 ina input input signal-ttl or cmos compatible. 6 ena enable the system enable pin. this pin, when driven low, disables the chip, forcing high im pedance state to the output. 22-24 outa output driver output. for application purposes, this pin is connected to the gate of a mosfet. in som e applications, a low-im pedance series resistor m ay be required between this output and the m o s fe t g ate. 8 inb input input signal-ttl or cmos compatible. 9 enb enable the system enable pin. this pin, when driven low, disables the chip, forcing high im pedance state to the output. 19-21 outb output driver output. for application purposes, this pin is connected to the gate of a mosfet. in som e applications, a low-im pedance series resistor m ay be required between this output and the m o s fe t g ate. 5,10 15-18 25-28 gnd ground the system ground pins. internally connected to all circuitry, these pins provide ground reference for the entire chip. all of these pins should be connected to a low noise analog ground plane for optim um perform ance. pin configurations and package outline ordering information part number package type temp. range grade IXDD415SI 28-pin soic -40 c to +85 c industrial note: bottom-side heat sinking metalization is connected to ground
4 IXDD415SI typical performance characteristics v in figure 2a - characteristics test diagram rise time vs. load capacitance v cc = 15v, v oh = 2v to 12v load capacitance (pf) 1k 2k 3k 4k 0 rise time (ns) 0 1 2 3 4 5 fig. 3 fall time vs. load capacitance v cc = 15v, v oh = 12v to 2v load capacitance (pf) 1k 2k 3k 4k 0 fall time (ns) 0 1 2 3 4 5 fig. 4 supply current vs. frequency vcc=15v frequency (mhz) 5 10152025 supply current (ma) 0 1000 2000 3000 4000 4 nf 2 nf 1 nf c l = 0 fig. 5 supply current vs. load capacitance vcc=15v load capacitance (pf) 0k 1k 2k 3k 4k supply current (ma) 0 1000 2000 3000 4000 1 mhz 5 mhz 10 mhz 20 mhz 15 mhz 25 mhz fig. 6 figure 2b - timing diagram input output 5v 90% 2.5v 10% 0v 0v vcc 90% 10% t ondly t offdly t r t f pw min
5 IXDD415SI propagation delay vs. supply voltage c l =4nf v in =5v@100khz suppl y vol tage (v) 8 1012141618 propagation delay (ns) 0 10 20 30 40 50 t ondly t offdly fig. 7 propagation delay vs. input voltage c l =4nf v cc =15v input voltage (v) 24681012 propagation delay (ns) 0 10 20 30 40 50 t ondly t offdly fig. 8 propagation delay vs. junction temperature c l =4nf, v cc =15v tem p erature ( c ) -40-200 20406080100120 time (ns) 10 15 20 25 30 35 40 45 50 t offdly t ondly fig. 9 figure 10 2.2ns rise time figure 11 <6ns minimum pulse width typical output waveforms unless otherwise noted, all waveforms are taken driving a 1nf load, 1mhz repetition frequency, v cc =15v, case temperature = 25 c
6 IXDD415SI figure 14 - high frequency gate drive circuit figure 12 500khz cw repetition frequency figure 13 50mhz burst repetition frequency
7 IXDD415SI applications information high frequency gate drive circuit the circuit diagram in figure 14 is a circuit diagram for a very high switching speed, high frequency gate driver circuit using the IXDD415SI. this is the circuit used in the evdd415 evaluation board,and is capable of driving a mosfet at up to the maximum operating limits of the ixdd415. the circuit's very high switching speed and high frequency operation dictates the close attention to several important issues with respect to circuit design. the three key elements are circuit loop inductance, vcc bypassing and grounding. circuit loop inductance referring to figure 14, the vcc to vcc ground current path defines the loop which will generate the inductive term. this loop must be kept as short as possible. the output leads (pins 24, 23, 22, 21, 20, and 19) must be no further than 0.375 inches (9.5mm) from the gate of the mosfet. furthermore the output ground leads (pins 25, 26, 27 and 28 on one end of the ic and pins 15, 16, 17, and 18 on the other end of the ic) must provide a balanced symmetric coplanar ground return for optimum operation. vcc bypassing in order for the circuit to turn the mosfet on properly, the ixdd415 must be able to draw up to 15a of current per output channel from the vcc power supply in 2-6ns (depending upon the input capacitance of the mosfet being driven). this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is at least two orders of magnitude larger than the load capacitance. usually, this is achieved by placing two or three different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected, low inductance, low resistance, high-pulse current-service capacitors). care should be taken to keep the lengths of the leads between these bypass capacitors and the ixdd415 to an absolute minimum. the bypassing should be comprised of several values of chip capacitors symmetrically placed on ether side of the ic. recommended values are .01uf, .47uf chips and at least two 4.7uf tantalums. grounding in order for the design to turn the load off properly, the ixdd415 must be able to drain this 15a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixdd415 and its load. path #2 is between the ixdd415 and its power supply. path #3 is between the ixdd415 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and its load as short and wide as possible, and treated as coplanar transmission lines. in configurations where the optimum configuration of circuit layout and bypassing cannot be used, a series resistance of a few ohms in the gate lead may be necessary to prevent ringing. heat sinking for high power operation, the bottom side metalized heat sink pad should be epoxied to the circuit board ground plane, or attached to an appropriate heat sink, using thermally conductive epoxy. the heat sink tab is connected to ground. figure 15: IXDD415SI bottom side heat sinking metalization
8 IXDD415SI ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com directed energy, inc. an ixys company 2401 research blvd. ste. 108, ft. collins, co 80526 tel: 970-493-1901; fax: 970-493-1903 e-mail: deiinfo@directedenergy.com www.directedenergy.com the enable (en) input to the ixdd415 is a high voltage cmos logic level input where the en input threshold is ? v cc , and may not be compatible with 5v cmos or ttl input levels. the ixdd415 en input was intentionally designed for enhanced noise immunity with the high voltage cmos logic levels. in a typical gate driver application, v cc =15v and the en input threshold at 7.5v, a 5v cmos logical high input applied to this typical ixdd415 application?s en input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. the note below is for optional adaptation of ttl or 5v cmos levels. the circuit in figure 16 alleviates this potential logic level misinterpretation by translating a ttl or 5v cmos logic input to high voltage cmos logic levels needed by the ixdd415 en input. from the figure, v cc is the gate driver power supply, typically set between 8v to 20v, and v dd is the logic power supply, typically between 3.3v to 5.5v. resistors r1 and r2 form a voltage divider network so that the q1 base is posi- tioned at the midpoint of the expected ttl logic transition levels. a ttl or 5v cmos logic low, v ttllow =~<0.8v, input applied to the q1 emitter will drive it on. this causes the level translator output, the q1 collector output to settle to v cesatq1 + v ttllow =<~2v, which is sufficiently low to be correctly interpreted as a high voltage cmos logic low (<1/3v cc =5v for v cc =15v given in the ixdd415 data sheet.) a ttl high, v ttlhigh =>~2.4v, or a 5v cmos high, v 5vcmoshigh =~>3.5v, applied to the en input of the circuit in figure 16 will cause q1 to be biased off. this results in q1 collector being pulled up by r3 to v cc =15v, and provides a high voltage cmos logic high output. the high voltage cmos logical en output applied to the ixdd415 en input will enable it, allowing the gate driver to fully function as a 15 ampere output driver. the total component cost of the circuit in figure 16 is less than $0.10 if purchased in quantities >1k pieces. it is recommended that the physical placement of the level translator circuit be placed close to the source of the ttl or cmos logic circuits to maximize noise rejection. ttl to high voltage cmos level translation 10k r3 3.3k r2 q1 2n3904 en output cc (from gate driver power supply) input) ttl cmos 3.3k r1 v dd (from logic power supply) or hi g h volta ge (to ixdd415 en input) figure 16 - ttl to high voltage cmos level translator doc #9200-0233 r2
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